This invention relates to methods and systems for data storage on Programmable Logic Devices (PLDs). More particularly, this invention relates to configuring data storage on PLDs in a versatile fashion. U.S. Pat. No. 6,144,573 describes memory circuits and is hereby incorporated by reference herein in its entirety.
Designs that are implemented in Programmable Logic Devices (PLDs) often require RAM blocks of various sizes. Some designs require relatively shallow, wide RAM—e.g., 16 bits wide by 256 words deep—, while some designs require relatively deep, narrow RAM—e.g., 1 bit wide by 4K words deep—, and some designs require an odd mixture of the two.
In order to implement RAM efficiently, PLDs may contain dedicated circuitry for implementing RAM blocks.
It would be desirable to provide an improved circuitry and methods for implementing RAM in a PLD. It would also be desirable to provide circuitry and methods for reducing the amount of routing resources required when using the extremely wide RAMs.